The present invention relates to an integrated circuit device. More particularly, the present invention relates to an integrated circuit device having a through-silicon via (TSV) and an auxiliary structure proximate to the TSV for reducing the thermal influence from the operating heat of the active element.
Packaging technology for integrated circuit devices has been continuously improved to meet the demand for miniaturization and mounting reliability. Recently, as the miniaturization and high functionality of electric and electronic products are required, various techniques have been disclosed in the art.
By using a stack of at least two chips, in the case of a memory device for example, it is possible to produce a product having a memory capacity which is twice as large as that obtainable through semiconductor integration processes. Also, a stacked package provides advantages not only of an increase in memory capacity but also in regards to mounting density and mounting area utilization efficiency. Due to such advantages, research and development of stacked package technology has accelerated.
As an example of a stacked package, a through-silicon via (TSV) has been disclosed in the art. The stacked package using a TSV has a structure in which the TSV is disposed in a chip so that chips are physically and electrically connected with each other through the TSV. Generally, a TSV is formed by etching a vertical via through a substrate and filling the via with a conductive material, such as copper. To increase the transmission speed and for high-density fabrication, the thickness of a semiconductor wafer comprising multiple integrated circuit devices each having the TSV should be reduced.